LatticeECP2/M

With up to 95K LUTS, up to 5.3 Mbit block and distributed RAM, the LatticeECP2/M families integrate capabilities previously only found on higher cost FPGAs.

Redefining the FPGA application space – With up to 95 K LUTs and up to 5.3 Mbit block and Distributed RAM the LatticeECP2 and LatticeECP2M families integrate capabilities previously only found on higher cost FPGAs.

High speed SERDES with PCS – High jitter tolerant, low transmission SERDES with PCS blocks can be configured to support an array of popular data protocols including PCI Express, Ethernet (1 GbE and SGMII), OBSAI and CPRI.

Performance without the power drain – Using just 0.35 W static power, you’d be forgiven for thinking that the LatticeECP2/M families couldn’t support up to 840 Mbps LVDS IO, DDR1/2 at 533 Mbps, and SPI4.2 at 750 Mbps – but they can.

Features

Embedded SERDES supports data rates up to 3.125 Gbps (LatticeECP2M only)

Up to 42 sysDSP™ blocks for high performance multiply and accumulate

55 Kbits to 5308 Kbits sysMEM™ Embedded Block RAM (EBR)

sysCLOCK Analog PLLs and DLLs enable clock multiply, divide, phase & delay adjust

Available in TQFP, PQFP and fpBGA, packages

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